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? semiconductor components industries, llc, 2006 october, 2006 ? rev. p1 1 publication order number: NB4L339/d NB4L339 2.5 v / 3.3 v differential 2:1 clock in to differential lvpecl clock generator / divider / fan?out buffer multi ? level inputs w/ internal termination description the NB4L339 is a multi ? function clock generator featuring a 2:1 clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; 1/ 2/ 4/ 8. one divide block has a choice of 1 or 2. the output of each divider block is fanned ? out to two identical differential lvpecl copies of the selected clock. all outputs provide standard lvpecl voltage levels when externally terminated with a 50 ? ohm resistor to v cc ? 2 v. the differential clock inputs incorporate internal 50 ? termination resistors and will accept lvpecl, cml or lvds logic levels. the common output enable pin (en ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip ? flop is clocked on the falling edge of the input clock. therefore, all associated specification limits are referenced to the negative edge of the clock input. this device is housed in a 5x5 mm 32 pin qfn package. features ? maximum input/output clock frequency > 700 mhz ? low skew lvpecl outputs, 15 ps typical ? 1 ns typical propagation delay ? 150 ps typical rise and fall times ? 0.15 ps typical rms phase jitter ? 0.5 ps typical rms random clock period jitter ? lvpecl, cml or lvds input compatible ? operating range: v cc = 2.375 v to 3.6 v with v ee = 0 v ? lvpecl output level; 750 mv peak ? to ? peak, typical ? internal 50 ? input termination provided ? synchronous output enable/disable ? asynchronous master reset ? functionally compatible with existing 2.5 v / 3.3 v lvel, lvep, ep, and sg devices ? ? 40 c to 85 c ambient operating temperature ? 32 ? pin qfn, 5 mm x 5 mm ? this is a pb ? free device qfn32 mn suffix case 488am see detailed ordering and shipping information on page 11 of this data sheet. ordering information marking diagram http://onsemi.com 32 1 NB4L339 awlyyww 1 a = assembly location wl = wafer lot yy = year ww = work week = pb ? free package figure 1. simplified block diagram (note: microdot may be in either location) 4 .com datasheet u
NB4L339 http://onsemi.com 2 figure 2. detailed logic diagram divsel clksel clka vta clka clkb vtb clkb en mr 50 ? 50 ? 50 ? 50 ? example: fin = 622.08 mhz a 1 / 2 r b 2 r c 4 r d 8 r en qa0 qa0 qa1 qa1 a fouta = 622.08 mhz or 311.04 mhz qb0 qb0 qb1 qb1 b foutb = 311.04 mhz qc0 qc0 qc1 qc1 c foutc = 155.52 mhz qd0 qd0 qd1 qd1 d foutd = 77.76 mhz clksel* clk input selected 0 clka 1 clkb table 1. input select function table divsel* qa divide 0 divide by 1 1 divide by 2 table 2. divider select function table clk input function low to high transition divide ? outputs active high to low transition hold q ? outputs inactive table 3. clock enable/disable function table x (don?t care) en *mr ** h 0 h 1 l x (don?t care) reset q * pin will default low when left open. ** pin will default high when left open. figure 3. pinout qfn ? 32 (top view) NB4L339 qb0 qb0 qb1 qb1 qc0 qc0 qc1 qc1 v ee clka vta clka clkb vtb clkb v ee v cc divsel qa0 qa0 qa1 qa1 mr v cc v cc clksel qd1 qd1 qd0 qd0 en v cc exposed pad (ep) 32 31 30 29 28 27 26 25 9 10 111213141516 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 4 .com datasheet u
NB4L339 http://onsemi.com 3 table 4. pin description pin name i/o description 1, 8, ep v ee ? negative supply voltage 2 clka lvpecl, cml, lvds input non ? inverted differential input (a). (note 1) 3 vta ? internal 100 ? c enter ? tapped termination pin for clka and clka (note 1). 4 clka lvpecl, cml, lvds input inverted differential input (a). (note 1) 5 clkb lvpecl, cml, lvds input non ? inverted differential input (b). (note 1) 6 vtb ? internal 100 ? c enter ? tapped termination pin for clkb and clkb . (note 1) 7 clkb lvpecl, cml, lvds input inverted differential input (b). (note 1) 9, 16, 25, 32 v cc ? positive supply voltage 10 clksel lvcmos/lvttl asynchronous clock input select pin. this pin defaults low when left open with 80 k resistor to v ee . 11 qd1 lvpecl output inverted differential (d1) output. typically terminated with 50 resistor to v cc ? 2 v 12 qd1 lvpecl output non ? inverted differential (d1) output. typically terminated with 50 resistor to v cc ? 2 v. 13 qd0 lvpecl output inverted differential (d0) output. typically terminated with 50 resistor to v cc ? 2 v. 14 qd0 lvpecl output non ? inverted differential (d0) output. typically terminated with 50 resistor to v cc ? 2 v. 15 en lvcmos/lvttl synchronous output enable/disable pin. this pin defaults low when left open with 80 k resistor to v ee . 17 qc1 lvpecl output inverted differential (c1) output. typically terminated with 50 resistor to v cc ? 2 v. 18 qc1 lvpecl output non ? inverted differential (c1) output. typically terminated with 50 resistor to v cc ? 2 v. 19 qc0 lvpecl output inverted differential (c0) output. typically terminated with 50 resistor to v cc ? 2 v. 20 qc0 lvpecl output non ? inverted differential (c0) output. typically terminated with 50 resistor to v cc ? 2 v. 21 qb1 lvpecl output inverted differential (b1) output. typically terminated with 50 resistor to v cc ? 2 v. 22 qb1 lvpecl output non ? inverted differential (b1) output. typically terminated with 50 resistor to v cc ? 2 v. 23 qb0 lvpecl output inverted differential (b0) output. typically terminated with 50 resistor to v cc ? 2 v. 24 qb0 lvpecl output non ? inverted differential (b0) output. typically terminated with 50 resistor to v cc ? 2 v. 26 mr lvcmos/lvttl master reset asynchronous. this pin defaults high when left open with 80 k resistor to v cc . 27 qa1 lvpecl output inverted differential (a1) output. typically terminated with 50 resistor to v cc ? 2 v. 28 qa1 lvpecl output non ? inverted differential (a1) output. typically terminated with 50 resistor to v cc ? 2 v. 29 qa0 lvpecl output inverted differential (a0) output. typically terminated with 50 resistor to v cc ? 2 v. 30 qa0 lvpecl output non ? inverted differential (a0) output. typically terminated with 50 resistor to v cc ? 2 v. 31 divsel lvcmos/lvttl asynchronous divide select pin selects a divide block outputs to divide by 1 or divide by 2. defaults low when left open, divide ? by ? 1, with 80 k resistor to v ee . ? ep ? exposed pad. the exposed pad (ep) on package bottom (see case drawing) is thermally connected to the die for improved heat transfer out of package and must be attached to a heat ? sinking conduit. the pad is electrically connected to v ee and must be connected to v ee on the pc board. 1. in the dif ferential configuration when the input termination pin (vtx / vtx ) are connected to a common termination voltage or left open, and if no signal is applied on clkx / clkx input then the device will be susceptible to self ? oscillation. 4 .com datasheet u
NB4L339 http://onsemi.com 4 table 5. attributes characteristics value input default state resistors 80 k esd protection human body model machine model > 2.0 kv > 100 v moisture sensitivity (note 2) qfn ? 32 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 366 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 6. maximum ratings symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 4.0 v v io input/output voltage v ee = 0 v ? 0.5 = v io v cc + 0.5 4.0 v v inpp differential input voltage swing |clk ? clk | 2.8 v i in input current through r t (50 resistor) static surge 45 80 ma i out output current continuous surge 50 100 ma t a operating temperature range qfn ? 32 ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfpm 500 lfpm qfn ? 32 qfn ? 32 31 27 c/w jc thermal resistance (junction ? to ? case) (note 3) qfn ? 32 12 c/w t sol wave solder (pb ? free) 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad. 4 .com datasheet u
NB4L339 http://onsemi.com 5 table 7. dc characteristics, clock inputs, lvpecl outputs v cc = 2.375 v to 3.6 v, v ee = 0 v, t a = ? 40 c to +85 c (note 5) symbol characteristic min typ max unit i ee power supply current (inputs and outputs open) 58 70 90 ma lvpecl outputs (note 4) v oh output high voltage v cc = 3.3 v v cc = 2.5 v v cc ? 1135 2155 1355 v cc ? 1020 2280 1480 v cc ? 760 2540 1740 mv v ol output low voltage v cc = 3.3 v v cc = 2.5 v v cc ? 1935 1355 555 v cc ? 1770 1530 730 v cc ? 1560 1740 940 mv differential input driven single ? ended (see figures 6 & 8) vth input threshold reference voltage range (note 6) 1125 v cc ? 75 mv v ih single ? ended input high voltage vth + 75 v cc mv v il single ? ended input low voltage v ee vth ? 75 mv v ise single ? ended input voltage (v ih ? v il ) 150 2800 mv differential inputs driven differentially (see figures 7 & 9) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage v ee v cc ? 150 mv v cmr input common mode range (differential configuration) (note 8) 1125 v cc ? 75 mv v id differential input voltage swing (v ihd ? v ild ) 150 2800 mv i ih input high current clkx / clkx (vtx open) 10 40 a i il input low current clkx / clkx (vtx open) ? 10 10 a single ? ended lvcmos / lvttl control inputs v ih single ? ended input high voltage 2000 v cc mv v il single ? ended input low voltage v ee 800 mv i ih input high current clksel, divsel, en mr 40 ? 10 115 10 a i il input low current clksel, divsel, en mr ? 10 ? 11 5 10 ? 40 a termination resistors r tin internal input termination resistor (measured across clkx and clkx ) 80 100 120 r tin internal input termination resistor (measured from clkx to vtx) 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. lvpecl outputs require 50 receiver termination resistors to v cc ? 2 v for proper operation. 5. input and output parameters vary 1:1 with v cc . 6. vth is applied to the complementary input when operating in single ? ended mode. 7. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 8. v cmr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the dif ferential input signal. 4 .com datasheet u
NB4L339 http://onsemi.com 6 table 8. ac characteristics v cc = 2.375 v to 3.6 v, v ee = 0 v (note 9) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max fin max maximum input clock frequency 700 700 700 mhz v outpp output voltage amplitude (@ v inppmin ) (see figure 4) f in 622 mhz 530 730 530 730 530 730 mv t plh , t phl propagation delay to clkx/clkx to qx/qx output differential 1mr to qx 0.8 1.2 1 ? 1.3 5.0 0.8 1.2 1 ? 1.3 5.0 0.8 1.2 1 ? 1.3 5.0 ns trr reset recovery 3.0 3.0 3.0 ns dco output clock duty cycle all divides 40 60 40 60 40 60 % t skew duty cycle skew @ 50 mhz (note 10) within device skew (note 11) device to device skew (note 12) 20 30 90 50 60 190 20 30 90 50 60 190 20 30 90 50 60 190 ps t s setup time @ 50 mhz en to clkx divsel to clkx 900 ? 100 900 ? 100 900 ? 100 ps t h hold time @ 50 mhz clkx to en clkx to divsel 800 0 800 0 800 0 ps t pw minimum pulse width mr 5.0 5.0 5.0 ns n phase noise f in = 622.08 mhz outputs (a) div by 1 10 khz 100 khz 1 mhz 10 mhz 20 mhz 40 mhz ? 136 ? 136 ? 141 ? 141 ? 141 ? 141 dbc t jit1 phase jitter (figure 4) f in = 622.08 mhz, 12 khz ? 20 mhz offset all divides 0.15 0.25 0.15 0.25 0.15 0.25 ps rms t jit2 random clock period jitter (note 13) f in = 622.08 mhz all divides 0.5 1.5 0.5 1.5 0.5 1.5 ps rms v inpp input voltage swing/sensitivity (differential configuration) (note 14) 150 150 150 mv t r , t f output rise/fall times @ 622.08 mhz input frequency (20% ? 80%) 150 250 150 250 150 250 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. measured by forcing v inpp (min) from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc ? 2 v input edge rates 100 ps (20% ? 80%). 10. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 50 mhz. 11. skew is measured between outputs under identical transitions and conditions. duty cycle skew is defined only for differential operation when the delays are measured from the cross ? point of the inputs to the cross ? point of the outputs. 12. device to device skew is measured between outputs under identical transition @ 50 mhz. 13. additive rms jitter with 50% duty cycle clock signal; all inputs and outputs active. 14. v inpp (max) cannot exceed v cc ? v ee . input voltage swing is a single ? ended measurement operating in differential mode. 4 .com datasheet u
NB4L339 http://onsemi.com 7 figure 4. NB4L339 vs. agilent 8665a 622.08 mhz at 3.3 v, room ambient figure 5. output voltage amplitude (v outpp ) vs. input clock frequency (f in ) at ambient temperature (typical) f out , clock output frequency (ghz) v outpp , output voltage amplitude (mv) (typical) 700 600 500 400 300 200 100 0 1.2 0.1 0 1.0 800 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 application information the NB4L339 is a high ? speed, clock multiplexer , divider and low skew fan ? out buffer featuring a 2:1 clock multiplexer front end and outputs a selection of four different divide ratios; 1/2/4/8. one divide block has a choice of 1 or 2. the outputs of all four divider blocks are fanned ? out to two pair of identical differential lvpecl copies of the selected clock. all outputs provide standard lvpecl voltage levels when externally terminated with a 50 ? ohm resistor to v tt = v cc ? 2 v. the differential clock input buffers incorporate internal 50 ? termination resistors in a 100 ? center ? tapped configuration and are accessible via a vtx pin. this feature provides transmission line termination on ? chip, at the receiver end, eliminating external components. inputs clka/b and clka /b must be signal driven or auto oscillation may result. the NB4L339 clock inputs can be driven by a variety of differential signal level technologies including lvds, lvpecl, or cml. the internal dividers are synchronous to each other. therefore, the common output edges are precisely aligned. the output enable pin (en ) is synchronous so that the internal divider flip ? flops will only be enabled/disabled when the internal clock is in the low state. this avoids any chance of generating a runt pulse on the internal clock when the device is enabled/disabled, as can happen with an asynchronous control. the internal enable flip ? flop is clocked on the falling edge of the input clock. therefore, all associated specification limits are referenced to the negative edge of the clock input. the master reset (mr ) is asynchronous. when mr is forced low, all q outputs go to logic low. 4 .com datasheet u
NB4L339 http://onsemi.com 8 figure 6. timing diagram mr clk q ( 1) q ( 2) q ( 4) q ( 8) figure 7. master reset timing diagram note: on the rising edge of mr , q goes high after the first rising edge of clk, following a high ? to ? low clock transition. clk mr q ( n) t rr t rr figure 8. output enable timing diagrams clk q ( n) en internal clock disabled internal clock enabled the en signal will ?freeze? the internal divider flip ? flops on the first falling edge of clk after its assertion. the internal divider flip ? flops will maintain their state during the freeze. when en is deasserted (low), and after the next falling edge of clk, then the internal divider flip ? flops will ?unfreeze? and continue to their next state count with proper phase relationships. 4 .com datasheet u
NB4L339 http://onsemi.com 9 figure 9. input structure figure 10. differential input driven single ? ended figure 11. v th diagram figure 12. differential inputs driven differentially figure 13. differential inputs driven differentially figure 14. vcmr diagram figure 15. ac reference measurement note: v ee v in v cc ; v ih > v il v ihd v ild v id = |v ihd(clk) ? v ild(clk) | clk clk clk v th clk clk clk clk clk q q t plh t phl v inpp = v ih (clk) ? v il (clk) v outpp = v oh (q) ? v ol (q) 50 50 clkn vtn clkn v cc v ee v thmin v thmax vth clk v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v ee v cmmax v cmmax v cmr clk clk v ihdmax v ildmax v id = v ihd ? v ild v ihdtyp v ildtyp v ihdmin v ildmin v th 4 .com datasheet u
NB4L339 http://onsemi.com 10 v cc lvpecl driver clkx 50 z o = 50 z o = 50 50 clkx NB4L339 v cc v cc cml driver clkx 50 z o = 50 z o = 50 50 clkx NB4L339 v cc v t = v cc figure 16. lvpecl interface figure 17. lvds interface v t = v cc ? 2.0 v figure 18. standard 50 load cml interface v cc lvds driver clkx 50 z o = 50 z o = 50 50 clkx NB4L339 v cc v t = open gnd gnd gnd gnd gnd gnd v cc differential driver clkx 50 z o = 50 z o = 50 50 clkx NB4L339 v cc v t = v refac * figure 19. capacitor ? coupled differential interface (v t connected to external v refac ) v cc single ? ended driver clkx (open) 50 z o = 50 50 clkx NB4L339 v cc gnd gnd gnd gnd v t = v refac * figure 20. capacitor ? coupled single ? ended interface (v t connected to external v refac ) *v refac bypassed to ground with a 0.01 f capacitor. clkx clkx 4 .com datasheet u
NB4L339 http://onsemi.com 11 figure 21. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices) q d driver device receiver device 50 50 q d v tt v tt = v cc ? 2.0 v z o = 50 z o = 50 ordering information device package shipping ? NB4L339mng qfn ? 32 (pb ? free) 74 units / tray NB4L339mnr2g qfn ? 32 (pb ? free) 1000 / tape & reel *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 4 .com datasheet u
NB4L339 http://onsemi.com 12 package dimensions qfn32 5*5*1 0.5 p case 488am ? 01 issue o seating 32 x k 0.15 c (a3) a a1 d2 b 1 9 16 17 32 2 x 2 x e2 32 x 8 24 32 x l 32 x bottom view exposed pad top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e a 0.10 b c 0.05 c notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm terminal 4. coplanarity applies to the exposed pad as well as the terminals. plane dim min nom max millimeters a 0.800 0.900 1.000 a1 0.000 0.025 0.050 a3 0.200 ref b 0.180 0.250 0.300 d 5.00 bsc d2 2.950 3.100 3.250 e 5.00 bsc e2 e 0.500 bsc k 0.200 ??? ??? l 0.300 0.400 0.500 2.950 3.100 3.250 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 3.20 0.28 3.20 32 x 28 x 0.63 32 x 5.30 5.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NB4L339/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative 4 .com datasheet u

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